Pitch shifting delay

[VREEEEVROOOOOW]

Yeah, I mean, mode 7… right?

[Pladask]

I have a pitch shifter delay program for the spin FV-1 platform for that I don't have any plans for. If people want I can post it here. I won't build it, but you can run it on spin FV-1 based pedals if you know how to write to EEPROMs.

[oldangelmidnight]

I have a pitch shifter delay program for the spin FV-1 platform for that I don't have any plans for. If people want I can post it here. I won't build it, but you can run it on spin FV-1 based pedals if you know how to write to EEPROMs.

I'd like a chance to mess around with it.

[Pladask]

Here ya go:

NSFW: show

; Pitch shifting delay
;
; pot0 adjusts delay time
; pot1 adjusts pitch shift (+/- 1 octave)
; pot2 feedback amout

equ length 26600 ; Delay length in samples
equ smooth 0.000125 ; Smoothness coeff

mem echo length ; Echo delay
mem pidel 4096 ; pitch delay
mem temp 1 ; Temp location for partial reg calc

equ del_read reg0 ; for address pointer of echo

; Initialization ##########################################################

skp RUN, loop
clr
wrax del_read, 0 ; Clear reg0 on startup
wldr RMP0, 0, 4096 ; Load rmp0 w. amplitude equal to pidel
loop:

; Delay time setup ######################################################
;
; Select tap from delay based on pot0, should range 0 to length
; Since pot only has 512 states, want to filter pot to avoid jumping
; Smooth POT0

clr ; Clear the ACC
or length * 256 ; Put delay length into ACC alligned to ACC[22:8]
mulx POT0 ; Multiply by POT0, new target value
rdfx del_read, smooth ; Smooth it : (target - current) * C + current
wrax del_read, 0 ; Write to reg, clear acc

; Audio signal flow ########################################################

ldax feed ; read feedback audio
mulx POT2 ; * feedback volume ctrl
rdax ADCL, 1 ; Add audio input

wra echo, 0 ; Write to start of the echo mem, clear acc

rdax del_read, 1.0 ; Get the delay tap to read
wrax addr_ptr, 0 ; Write it to the address pointer register
rmpa 1 ; Read from memory
wra pidel, 0 ; Write to pitch shift delay, clear acc

cho rda, RMP0, REG|COMPC, pidel ; (1-k) * sample[addr]
cho rda, RMP0,, pidel+1 ; k * sample[addr+1] + ACC
wra temp, 0 ; Write to temp, clear acc

cho rda, RMP0, RPTR2|COMPC, pidel ; (1-k) * sample[addr+ half ramp]
cho rda, RMP0, RPTR2, pidel+1 ; k * sample[addr+ half ramp + 1] + ACC

cho sof, RMP0, NA|COMPC, 0 ; ACC*(1-XFADE) + 0
cho rda, RMP0, NA, temp ; Memory[addr] * XFADE + ACC

wrax DACL, 1 ; Write to DACL, keep in acc
wrax feed, 0 ; write to feedback reg, clear acc

; Rate adjustment : ##########################################################

ldax POT1 ; Read POT0 into ACC
sof 1.0, -0.5 ; Subtract 0.5 so ACC ranges from -0.5 to +0.5

skp GEZ, pos ; If ACC >= 0, skip to "pos" label
sof 0.5, 0 ; ACC < 0, scale it to be -0.25 to 0
pos:

wrax RMP0_RATE,0 ; Write to ramp rate reg, clear acc

I haven't tested this version of the code. I replaced a clean/pitchshift balance parameter for a feedback knob (developed for FORM which has an analog feedback knob).

Original code without feedback knob (tested):

NSFW: show

; pot0 adjusts delay time
; pot1 adjusts pitch shift (+/- 1 octave)
; pot2 clean delay / pitch shift delay mix

equ length 26600 ; Delay length in samples
equ smooth 0.000125 ; Smoothness coeff

mem echo length ; Echo delay
mem pidel 4096 ; pitch delay
mem temp 1 ; Temp location for partial reg calc
mem compdel 2048 ; Reduce clean/octave lag diff

equ del_read reg0 ; for address pointer of echo
equ clean reg1 ; Clean, delayed sound reg NOT IN USE

skp RUN, loop
clr
wrax del_read, 0 ; Clear reg0 on startup
wldr RMP0, 0, 4096 ; Load rmp0 w. amplitude equal to pidel
loop:

; Select tap from delay based on pot0, should range 0 to length
; Since pot only has 512 states, want to filter pot to avoid jumping
; Smooth POT0

clr ; Clear the ACC
or length * 256 ; Put delay length into ACC alligned to ACC[22:8]
mulx pot0 ; Multiply by POT0, new target value
rdfx del_read, smooth ; Smooth it : (target - current) * C + current
wrax del_read, 0 ; Write to reg, clear acc

ldax adcl ; Read audio input
wra echo, 0 ; Write to start of the echo mem, clear acc

rdax del_read, 1.0 ; Get the delay tap to read
wrax addr_ptr, 0 ; Write it to the address pointer register
rmpa 1 ; Read from memory
wra compdel, 1 ; Write to compensation delay
wra pidel, 0 ; Write to pitch shift delay, clear acc

cho rda, RMP0, REG|COMPC, pidel ; (1-k) * sample[addr]
cho rda, RMP0,, pidel+1 ; k * sample[addr+1] + ACC
wra temp, 0 ; Write to temp, clear acc

cho rda, RMP0, RPTR2|COMPC, pidel ; (1-k) * sample[addr+ half ramp]
cho rda, RMP0, RPTR2, pidel+1 ; k * sample[addr+ half ramp + 1] + ACC

cho sof, RMP0, NA|COMPC, 0 ; ACC*(1-XFADE) + 0
cho rda, RMP0, NA, temp ; Memory[addr] * XFADE + ACC

rda compdel#, -1.0 ; Add -clean to pitch shift
mulx pot2 ; Add mixer pot2
rda compdel#, 1.0 ; Add clean to pitch shift

wrax DACL, 0 ; Write to DACL, clear acc

; Rate adjustment :

ldax POT1 ; Read POT0 into ACC
sof 1.0, -0.5 ; Subtract 0.5 so ACC ranges from -0.5 to +0.5

skp GEZ, pos ; If ACC >= 0, skip to "pos" label
sof 0.5, 0 ; ACC < 0, scale it to be -0.25 to 0
pos:

wrax RMP0_RATE,0 ; Write to ramp rate reg, clear acc