ilovefuzz.com

[youtube]http://www.youtube.com/watch?v=XsjGXM48AEo[/youtube]

something like that

Why so close to the switches?

Other than that:

yikes


oh there is a slight spacing error on this test case but it won;t move upthat much, maybe a 1/4 inch . i guess it is close because there is a lot inside.

OOoooh dipswitches too?
I can't wait for this thing

Dipswitches were for expression/cv settings if i remember correctly

Is the PLL done through C? Curious if this is analog or not.

I have a curious idea in the back of my head, but even then it would be developing something in Pure Data. Don't know if a PLL can be made in PD.

DRodriguez wrote:Dipswitches were for expression/cv settings if i remember correctly

ya the 4 dips, 3 of them just make the 3 expression jacks appropriate for 0-5V CV or Expression, the last one flips the function of the lfo expression input, so it is either duty cycle or rate, since there was not enough room to add more expression jacks on the top.

Strange Tales wrote:Is the PLL done through C? Curious if this is analog or not.

I have a curious idea in the back of my head, but even then it would be developing something in Pure Data. Don't know if a PLL can be made in PD.

no this one is a mix i guess. there are some 8bit tiny pics for different tasks but the phase comparator/oscillator core is analog, so i would say it is still mostly analog pll. you could make a software pll though, why not.

I wish I could, not sure if I'm smart enough to understand the math behind PLLs though. The math behind it is fucking intense and might've killed my idea.

http://liquidsdr.org/blog/pll-howto/

I think most of the math revolves around the phase comparator section though.

Strange Tales wrote:I wish I could, not sure if I'm smart enough to understand the math behind PLLs though. The math behind it is fucking intense and might've killed my idea.

http://liquidsdr.org/blog/pll-howto/

I think most of the math revolves around the phase comparator section though.

What's your idea? Does it have to do with the PLL itself or something in Pure Data?

Most of the math on the page is talking about how to transfer an analog filter (paramaterized a certain way) into a typical digital filter structure (which has different parameters, but teh same response) i believe. the concept of how the coded pll works is the same as the analog one. im sure you could easily do it with experimentation as well.

This is some rad stuff! Duty cycle is equivalent to range, yeah?
Also welcome to the front page Scott!!